This is a brief description on how to create a post-fit timing simulation using Xilinx ISE WebPACK (using screen shots from version 9.1i).

In contrast to simple behavioral simulations, the post-fit simulation takes into account the delays introduced by signal runtimes on the chip. It therefore requires that you choose the same chip variant (especially concerning timing) which you would like to use in your final design.

For the simulation, we first have to create the input "stimulus" waveforms to be sent into the programmable logic device. The simulator will read in these and compute the expected output lines (as well as any internal connections).

Therefore, we need to add a new "test bench waveform" source to the project: I will call the file clock_test_bench:

After this, keep pressing Next and finally click on Finish and you will see a dialog to set up the fundamental characteristics:

For CPLDs without a main clock, use "Combinatorial (or internal clock)". The two times on the right are the most important: If you would like to be able to supply a clock signal with frequency f, you have to choose the check outputs and assign inputs time 1/(4f). For example, choose 6.25ns (6250ps) for a 40MHz clock. To be precise, the sum of both times (check outputs plus assign inputs) defines the minimum time interval between changes in input lines. A clock line at frequency f changes its state every 1/(2f) seconds, and keeping the "check" and "assign" times equally large results in 1/(4f). For additional granularity, you can make these times even smaller, of course.
Note: When changing the time scale, be sure to keep the GSR timing so that is stays 100ns (unless you know what you are doing).

Now you can create the desired simulation input by clicking on the cyan-colored bars in all input signal traces.
Note: In order to see the waveform in the source file tree on the left, you have to choose Sources for: Post-Fit Simulation.

The simulation input is now set up. In order to perform the actual simulation, double-click on Simulate Post-Fit Model in the Processes window.

After a while (don't get impatient!!), you will see the simulation result:

Some notes:

• When you change something in the source schematic and double-click on Simulate Post-Fit Model, then ISE is clever enough to go through all the synthesis steps as required and re-do the simulation.
• It seems that if you change something in the input waveform, you have to re-run Simulate Post-Fit Model to get new simulation results.
• The most important buttons are the blue ones to the left of the 1000 ns input in the screen shot.