Digital noise is a series of (more or less) random low/high pulses. Analog noise is an analog signal without any (apparent) order. There exist several types of noise, the most important ones being "white" noise, "pink" noise and "brown" noise.

White noise (which is not the same as Gaussian noise) is characterized by a flat spectrum, i.e. the signal has equal power in any frequency band (up to some bandwidth). Futhermore, it must have zero autocorrelation. For digital noise, this means that the the sequence of LOWs and HIGHs is statistically uncorrelated. (Especially this means that there is no period which, of course, is not true for simple digital noise sources as the one presented here.)

There exists a fairly simple way to create digital white noise using a shift register with n bits. Each clock pulse shifts the content one bit to the right and while the rightmost bit gets lost, the leftmost is filled up with an XOR combination of two other bits (a and b) from the shift register. The period and pulse distribution characteristics of the noise source are determined by which two bits are chosen.

In theory, it is possible to create a noise source with a period of up to 2ⁿ-1 when using a shift register with n bits. It is not 2ⁿ because the state with all bits set to 0 is special: The XOR feeds back a 0 at each clock cycle no matter which values for a and b are chosen. This means: If the state is "all 0", then it stays like that. One can show that if the state is different, it will never enter the "all 0" state.

This "all 0" state is unfortunate for circuit design because chips often provide a reset pin which sets all bits to 0. To circumvent the reset problem, I chose to not use XOR but instead XNOR (i.e. XOR with an inverter at the output). This, however, does not circumvent the principal problem of one degenerate state: In case all register locations are 1, the XNOR feeds back a 1 again. But in this case, we can easily start the noise source by resetting the shift register ICs.

The "shift register with XOR feedback" design is quite common in electronics literature (see e.g. Horowitz, Hill, "The Art of Electronics") and there exist tables describing which bits (a,b) to choose for optimum period at given shift register size n. Unfortunately, I could not find my XNOR variation in literature, so I had to choose the feedback bits a,b myself.

As the statement about irrecucibility in the Gaulois field for optimum period in Horowitz/Hill did not help me, I decided to simply simulate the shift register using a small self-written C program.

The main thing to test is of course the period length of the noise source. However, this is not all: For example using a=2 and b=5 results in a "noise source" with period 9 but when you look at the signal with an oscilloscope, it looks nothing like noise but simply like a normal square wave oscillator with a duty cycle of 30%. The reason is that this constellation produces just pulse lengths of 3 and 6 clock cycles, hence the period is 9 but the result is no white noise at all.

This demonstrates that the distribution of the produced pulse lengths needs to be considered as well to make sure that the output is actually white noise. Using a shift register with n bits, the longest pulse possible has a length of n clocks, appears only once per period and is LOW in the XNOR design (all bits 0) and HIGH in the XOR design (all bits 1).

The third thing to pay attention to is if the period is the maximum possible or not. In other words: If the produced noise depends on the initial value in the shift register. For example with a=2, b=22, the period is 2¹⁵-1 when starting with all zero. The maximum possible period of a shift register with length n=23 (which is obviously the minimum length which allows to use b=22) is, however, 2²²-1. This means that this setup will probably have other cycles possibly even with other period lengths, in case one starts with a value which is not one of the 2¹⁵-1 register states of the "primary" cycle. Since the "all 0" case is part of the primary cycle, the longest possible pulse is part of that cycle and all others have shorter maximum pulse lengths. As a consequence, such constellations do not produce optimum white noise (at least in the primary period, although in the above case, it comes pretty close). I want to call setups with maximum period "optimum".

I chose to use a shift register with a length of n=32. This can still be easily simulated using a recent PC (with periods up to 2³²-1 even the puls length histogram computation is completed within minutes). Based on my simulations, I chose to use a=2 and select the value of b among 8 possible values to allow for periods from 15 to 2³¹-1. Refer to the noise characteristics for more information about the noise produced by this circuit.

The design is fairly straightforward. There is a 20MHz clock source (crystal oscillator) to provide a base clock for the noise source. Switch S2 selects either this clock or an externally provided clock signal which is then fed into a divider. S5 allows to select a divisior of 1, 10 or 100 (or an OFF state). The resulting square wave then clocks a 32 bit shift register formed by IC1, IC2, IC3 and IC4.

Bit 0 of the shift register is used as noise output, bit 2 is the first feedback bit and HC4051 selects the second feedback bit from 8 possible ones. IC11, IC12 and everything right top of them is merely a channel 0..7 up/down selector with debounced keys and a 7 segment display. (It is not perfect: While switching "up" at state "7" will restart at "0", pressing "down" on "0" will stay at "0" and not continue with "7".)

IC5C/D and the AC04's on the right form an output stage which was experimentally verified to nicely drive into 50 Ohms (a single AC04 has a nominal output current of 24mA).

Finally, the circuitcy around IC13C is a debounced reset key allowing to reset the noise source at any time.

The board produces 2 complementary noise outputs which are delivered into two BNC connectors.

Frequency: With the built-in clock source of 20MHz, the base pulse length (shortest one) is 100ns.
The design has experimentally been verified to work stable up to 25MHz, the board begins to fail around 30MHz clock input.

Output: When terminated with 50 Ohms, the output rise/fall times were measured to be 4ns. The phase difference between the two outputs is below 1ns (I cannot measure it).

The presented noise source uses a shift register with a length of 32 bits (although only 31 bits are used) and allows to select 8 different periods ranging from 15 to 2³¹-1. The first feedback bit was selected as a=2, the second one is switchable in 8 steps choosing among b=3, 4, 6, 7, 9, 22, 19, 30.
The following table summarizes the facts: (See the theory part for the meaning of "optimum". Non-optimum noise is not completely white.)

As explained above, (white) digital noise is not only characterized by its period but also by a proper pulse length distribution. Here is the complete pulse length distribution of the presented noise source (start value is 0 for non-optimum modes):

m (a,b) | 0 (2,3)  1 (2,4)  2 (2,6)  3 (2,7)  4 (2,9)  5 (2,22)  6 (2,19)    7 (2,30) |      .
--------+-----------------------------------------------------------------------------+-------
 len  1 |       4        8       32       54      256      7738    262144   536870912 | len  1
 len  2 |       2        4       16       27      128      3961    131072   268435456 | len  2
 len  3 |       1        2        8       13       64      2077     65536   134217728 | len  3
 len  4 |       1        1        4        7       32      1011     32768    67108864 | len  4
 len  5 |                1        2        3       16       514     16384    33554432 | len  5
 len  6 |                         1        2        8       255      8192    16777216 | len  6
 len  7 |                         1        1        4       137      4096     8388608 | len  7
 len  8 |                                  1        2        80      2048     4194304 | len  8
 len  9 |                                           1        39      1024     2097152 | len  9
 len 10 |  .  .  .  .  .  .  .  .  .  .  .  .  .    1  .  .  19  .  . 512  .  1048576 | len 10
 len 11 |                                                    15       256      524288 | len 11
 len 12 |                                                    11       128      262144 | len 12
 len 13 |                                                     6        64      131072 | len 13
 len 14 |                                                     3        32       65536 | len 14
 len 15 |                                                     2        16       32768 | len 15
 len 16 |                                                     3         8       16384 | len 16
 len 17 |                                                     1         4        8192 | len 17
 len 18 |                                                     1         2        4096 | len 18
 len 19 |                                                     1         1        2048 | len 19
 len 20 |  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  .  1  .  .   1  .  .  1024 | len 20
 len 21 |                                                                         512 | len 21
 len 22 |                                                                         256 | len 22
 len 23 |                                                                         128 | len 23
 len 24 |                                                                          64 | len 24
 len 25 |                                                                          32 | len 25
 len 26 |                                                                          16 | len 26
 len 27 |                                                                           8 | len 27
 len 28 |                                                                           4 | len 28
 len 29 |                                                                           2 | len 29
 len 30 |                                                                           1 | len 30
 len 31 |                                                                           1 | len 31
--------+-----------------------------------------------------------------------------+-------
period  |      15       31      127      217     1023     32767   1048575  2147483647 |      .