Frequency counter: Input schematic

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IN-A/B and INV-A/B on the left top are the A,B inputs and A,B input inversion signals fed into an XOR gate.

The master mode selection switch is IC6 which switches the 4 mode LEDs (which also correspond to the measured unity, i.e. kHz, counts, milli-seconds or seconds) as well as the input for the divider and the counter: For standard frequency counter mode (mode: 0, unity: kHz) as well as counter mode (mode: 1, unity: counts), the input A is used (for divider, etc); for both time measurement modes (mode: 2,3; unity msec,seconds), the fixed 1MHz and 1kHz clock sources are used.

This, of course, requires that there is another switch which acts as a gate to control exactly how long the output of the master mode switch is conntected to the divider and counter: This is IC9C, an AND gate whose enable input (pin 10) is controlled by IC11: In counter and time measurement modes, this enable input is simply the AND (IC9A) of the measure signal from the logic board and the enable signal from the enable logic (left bottom in the sheet). For frequency counter mode, this enable logic has no use but here, the IC2A edge-triggered (D-type) flip-flop makes sure that the measurement actually starts at a HIGH-to-LOW transition of the input signal (this is the reason for the 2 inverters IC3A,B. When the measure signal from the logic board is LOW, the flip flop IC2A is reset (pin 1) and hence provides similar functionality as the IC9A AND gate for the other modes. frequency counter mode, the

In order to detect when measurement is finished, the "measuring done sensor" IC2B is used which triggers on the HIGH-to-LOW transition of the enable signal (IC11's pin 7). Especially note the "feedback loop" from pin 9 to pin 1 of IC11 which makes sure that once the measurement is finished (i.e. IC2B's pin 9 feeds HIGH into IC11's pins 10,12,13), it is not re-started again before there was a reset pulse on the reset line delivered by the logic board. (For obvious reason, no such feedback is provided for counter mode.)

For time measurement mode and frequency counter mode, IC14B plays an important role: It makes sure that the 1kHz oscillator starts running just at the time when the enable signal (IC11's pin 7) goes HIGH so that the n-th 1kHz clock tick is finished exactly n msec after the start of the measurement. (This holds also for frequency counter mode where the microcontroller on the logic board counts 100 to 10000 ticks of the 1kHz clock (i.e. gate times of 0.1 to 10 seconds) to decide when to end the measurement.) Otherwise an error of 0 to 1 msec would be introduced. Note also that no such synchronisation is provided for the 1MHz clock of the other (msec) time measurement mode which means that it always has an error of max. 1 usec. (This clock is also needed to clock the microcontroller on the logic board.)

In order to end a running measurement, either the logic board sets the enable signal to LOW (which is the only method for frequency counter mode: the microcontroller here uses the 1kHz clock for the gate timing) or when the enable logic (on the left bottom of the sheet) decides to do so. In any case, the microcontroller is informed about the end of the measurement via the measuing done signal on JP21.

The enable logic on the left bottom of the sheet is formed of the enable mode selector IC7 (with corresponding LEDs) and the 3 edge-triggered D-type flip-flops IC14, IC12A and IC12B. Enable mode 0 (standard) means "enable always" (IC7's pin 12) while mode 1 means "enable as long as input B is HIGH". The modes 2 and 3 are more complex: Mode 2 uses IC14 to make the enable signal change upon a LOW-to-HIGH transition of the input B. Note that the logic board has rough control over it since it provides the D input of the flip-flop. This allows to e.g. measure the time of 1, 10 or 100 pulses of some signal on input B by using the logic to count 0, 9 or 99 pulses and then set prolong (the D input) to LOW so that the next rising edge of input B will actually stop the measurement. Mode 3 finally allows to measure the time from the LOW-to-HIGH transition of input A to that of input B (or vice versa whichever comes first) by using the two edge-triggered flip-flops IC12A,B.

IC9B is the "hold logic" switch which makes sure that the counter content is not fed into the display latches as long as the hold signal is active. It is connected between the hwkey, logic board and the counter.

IC1D is an optional inverter between the divider output and the counter input which can be used to switch between rounding division and interger division (i.e. cut off); this signal is provided by the hwkey circuits.

Note that the jumper JP8, JP9, etc. are just there to provide signal decoupling on the PCB, i.e. to be able to disconnect parts more easily if needed.

Frequency Counter: Input Schematic